1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more specifically, to a semiconductor integrated circuit having a multiple-layered connection.
2. Description of the Prior Art
A structure of a multiple-layered connection has been recently employed in a certain type of a semiconductor integrated circuit to enhance the degree of integration of circuit elements by providing facility of connection. An example of such integrated circuit employing a multiple-layered connection is disclosed in Japanese Patent Publication Gazette No. 51-44871, wherein polyimide is employed as an interlayer insulating film.
FIG. 1 is a partial plan view of a conventional integrated circuit having a circuit pattern of a conventional two-channel amplifier circuit. It is pointed out that FIG. 1 shows in a simplified manner only an arrangement of connection runs of multiple electrode layers to be multiple-layered, while any other portions such as circuit elements of the integrated circuit are omitted in illustration for facility of understanding of the arrangement of the connection runs of the electrode layers to be multiple-layered. Referring to FIG. 1, a connection run 6 as a voltage source line for the voltage V.sub.cc is disposed in the central portion of a substrate 1 to extend in the horizontal direction, as viewed in FIG. 1, while a connection run 7 as a ground line for connection to the ground GND is disposed along the periphery of the three sides of the substrate 1. Although illustration was omitted, as well known, circuit elements such as transistors, resistors, diodes and the like, forming amplifier circuits of first and second channels, respectively, are formed in areas on the upper and lower sides, as viewed, of the voltage source line 6 of the semiconductor substrate 1. On the other hand, for the purpose of providing connections between the circuit elements in the upper and lower region, such as connections between the terminals A and A', the terminals B and B', the terminals C and C' and the like, connection runs 8 for mutual connection are formed. It is pointed out that the square terminals at both ends of these connection runs 8 are contacts for connection to the circuit elements concerned, although these circuit elements are not shown in FIG. 1.
As to be described subsequently in more detail, a first insulating film is formed on the main surface of the substrate 1 having the circuit elements formed thereon, the above described connection runs 6 and 7 and other connection runs for connection to the circuit elements are formed as a first electrode layer on the first insulating film in a predetermined pattern. A second insulating layer is then formed on the first insulating film and the first electrode layer and the connection runs 8 are then formed as a second electrode layer on the second insulating layer in a predetermined pattern for connection to the connection runs of the first electrode layer.
From the illustration in FIG. 1, it would be readily appreciated that a multiple-layered connection structure is required at the intersections between the connection run for the terminals D and D' and the connection run for the terminals E and E' and the intersection between the connection run for the terminals B and B' and the connection run for the terminals C and C'. To that end, a portion of the connection run 8 for the terminals E and E' is partially formed to be tunneled at an area 9 beneath the connection run 8 for the terminals D and D' and similarly a portion of the connection run 8 for the terminals C and C' is partially formed to be tunneled at an area 9 beneath the connection run 8 for the terminals B and B' to implement a multiple-layered connection structure. For the purpose of such tunneling connection to implement a multiple-layered connection structure at the areas 9, a portion of the first electrode layer is utilized, as to be described in more detail subsequently.
An example of such a multiple-layered connection structure is shown in FIG. 2, which is a sectional view of the integrated circuit shown in FIG. 1 taken along the line II--II in FIG. 1. Referring to FIG. 2, the multiple-layered connection structure will be described. It is pointed out that again for facility of illustration and understanding the circuit elements formed on the surface of the substate 1 are not shown in FIG. 2. The semiconductor substrate 1 having the circuit elements formed is covered with the first insulating layer 2 of silicon dioxide formed on the substate 1 and the first electrode layer 3 is formed in a predetermined pattern of the connection runs 9 as well as the connection runs 6 and 7 on the first insulating layer 2 by an evaporation process of aluminum, for example, such that any necessary connection runs 6 and 7 of the first electrode layer 3 maybe in contact with the circuit elements, not shown, through openings, not shown, formed in the first insulating layer 2. Then the second insulating layer 4 for interlayer insulation is provided on the first insulating layer 2 and the first electrode layer 3 and the second electrode layer 5 is formed thereon in a predetermined pattern of the connection runs 8 by an evaporation process of aluminum, for example.
Particularly in case of a semiconductor integrated circuit including a two-channel amplifier circuit, a power, increase is attempted in most cases through a balanced transformerless connection and a detection signal from the other channel is required in most cases, such as in case of a heat protecting circuit, an overvoltage protecting circuit, an area-of-safe-operation protecting circuit and the like. Accordingly, it could happen that an insulated cross arrangement is required between some two connection runs 8 of the second electrode layer 5. To that end, a portion of the first electrode layer 3 is utilized to form a lower layer of such insulated cross arrangement of two connection runs 8 of the second electrode layer 5. A structure of such insulated cross arrangement is implemented such that, as shown in FIG. 2, one connection run 8' of the second electrode layer 5 is tunneled by a portion 9 of the first electrode layer 3, while the other connection run 8" of the second electrode layer 5 is insulated by the second insulating layer 4.
However, in case of such a multiple-layered connection structure, a fundamental designing rule is adapted such that basically the connection runs of the first electrode layer 3 are utilized as much as possible to provide connection to the respective circuit elements so that the connections are made on substantially the whole surface, while those portions whose connection is not achieved by the connection runs of the first electrode layer 3 are connected through the connection runs of the second electrode layer 5. Accordingly, in providing an insulated cross arrangement of the connection runs of the second electrode layer 5, it is necessary to secure in advance an area;for tunneling by the use of a portion of the first electrode layer 3 as a lower layer, as shown in FIG. 2, which makes the designing complicated and could cause a case where the chip area need be made large for an area for tunneling.